The present invention relates generally to semiconductor devices and processes, and more particularly to a semiconductor device which has a downsized package structure of a Ball Grid Array (BGA) type, a Chip Size Package (CSP) type, or the like and which has reliable coupling with a mounting substrate.
FIG. 7 is a cross sectional view showing a semiconductor device having a conventional package structure which is disclosed in Japanese patent laid-open publication No. 11-243160 and which is hereafter referred to as prior art 1. In the structure shown in FIG. 7, a semiconductor chip 2 is bonded and fixed onto a Tape Automated Bonding (TAB) tape 1 via two layers comprising adhesive resin layers 3 and 4. Pads 5 provided on the TAB tape 1 are coupled, via holes formed in the TAB tape 1, with solder balls 6 which protrude from the lower surface of the TAB tape 1. Also, each electrode (not shown in the drawing) of the semiconductor chip 2 is coupled, via a bonding wire 8, with a bonding pad 7 formed on the TAB tape 1. The pads 5 and the bonding pads 7 are mutually coupled via wiring patterns (not shown in the drawing) formed on the TAB tape 1. Further, the semiconductor chip 2 is sealed or encapsulated with an encapsulation resin portion 9. A reference numeral 10 designates a hole for evacuating vapor or moisture.
FIG. 8 is a perspective view showing another conventional semiconductor device having different bump structure which is disclosed in Japanese patent laid-open publication No. 10-303244 and which is hereafter referred to as prior art 2. In the structure shown in FIG. 8, a plurality of pads 12 are formed on a semiconductor chip 11. Also, a plurality of bumps 13 are provided, each of which is disposed on the pad 12 and each of which protrudes at a predetermined angle from the pad 12 toward upside of the semiconductor chip 11. Each of the bumps 13 has a coupling portion 14 which contacts the pad 12, a wire portion 15 which extends from the coupling portion 14, and a terminal portion 16 which is formed on the top portion of the wire portion 15 and which has a round shape. The bumps 13 are covered by a thermosetting resin portion 17. The thermosetting resin portion 17 is partially polished away to expose only the top end portions of the bumps 13, i.e., the terminal portions 16.
The conventional bump structure shown in FIG. 8 is fabricated as follows. First, a wire is connected to each of the pads 12 by using a wire bonder. In this case, a round coupling portion 14 is formed at a portion on each of the pads 12 where the wire and the corresponding pad 12 are connected. Also, a round terminal portion 16 is formed at the upper end of each of wire portions 15. Thereafter, thermosetting resin 17 is supplied onto the semiconductor chip 11 such that the thermosetting resin 17 fills the space among the bumps 13. The thermosetting resin 17 is then cured and thereby the semiconductor chip 11 is encapsulated. Thereafter, the thermosetting resin 17 is polished to expose the terminal portion 16 of each of the bumps 13. Thereby, the semiconductor device having the bumps in which a length from each coupling portion 14 to the terminal portion 16 is relatively long.
However, in the semiconductor device having the package structure of the above-mentioned prior art 1, the TAB tape as the substrate 1 and adhesive, that is, the adhesive resin layers 3 and 4, are required. Also, in order to electrically couple from the semiconductor chip 2 to the solder balls 6 as external electrodes, it is necessary to use the bonding wires 8, the pads 7, wiring patterns (not shown in the drawing) on the TAB tape, and the pads 5. Therefore, the wiring structure becomes complicated and manufacturing costs of the package becomes high.
Also, in the semiconductor device having the package structure of the prior art 1, it is impossible obtain a BGA type package having approximately the same size as that of the semiconductor chip 2. Therefore, it is difficult to downsize the BGA package type semiconductor device.
On the other hand, in the semiconductor device having the package structure of the above-mentioned prior art 2, a substrate, adhesive and the like are not required. However, after filling the space among the bumps 13 with the thermosetting resin 17, it is necessary to polish the thermosetting resin 17 such that the spherical terminal portions 16 at the upper ends of the bumps 13 are exposed. Therefore, manufacturing process becomes complicated, and manufacturing costs become high.
Therefore, it is an object of the present invention to provide a semiconductor device having a reliable package structure which can be manufactured by a simple process and at low cost.
It is another object of the present invention to provide a semiconductor device having a reliable package structure which can be manufactured at low cost and which facilitates downsizing of the semiconductor device.
It is still another object of the present invention to provide a semiconductor device which has a package structure manufactured at low cost and providing high reliability of electrical connection between the semiconductor device and an external circuit.
It is still another object of the present invention to obviate the disadvantages of the package structures of the conventional semiconductor devices.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; a plurality of bonding pads formed on a surface of the semiconductor chip; a plurality of conductive wires each of which is coupled to the bonding pad and extends away from the surface of the semiconductor chip; a resin layer covering the surface of the semiconductor chip and covering the periphery the plurality of conductive wires, each of the conductive wires and the resin layer covering the periphery of the conductive wire forming a coaxial body; a plurality of solder balls each of which is mounted on the top end portion of the coaxial body and is electrically coupled with the conductive wire; and reinforcement resin portions each of which is attached to an area from an upper end portion of the coaxial body to the solder ball to reinforce the coupling of the solder ball with the coaxial body.
In this case, it is preferable that the reinforcement resin portions comprise resin material which is included in flux with resin used for coupling the solder balls to the conductive wires and which is left after a reflow process of the flux with resin.
It is also preferable that each of the conductive wires has a length of 300 to 1000 micrometers.
It is further preferable that the conductive wires extend vertically from the surface of the semiconductor chip.
It is advantageous that the coaxial body comprising the conductive wire and the resin layer covering the periphery of the conductive wire is deformable.
It is also advantageous that the conductive wires are made of gold or gold alloy.
It is further advantageous that, in the coaxial body comprising the conductive wire and the resin layer covering the periphery of the conductive wire, an upper end portion of the resin layer covering the conductive wire is removed by a predetermined depth to form a step portion, and the reinforcement resin portion is attached to an area from the step portion to the solder ball.
It is advantageous that the reinforcement resin portions comprise resin material which is included in flux with resin used for coupling the solder balls to the conductive wires and which is left after a reflow process of the flux with resin.
It is also advantageous that each of the conductive wires has a length of 300 to 1000 micrometers.
It is further advantageous that the conductive wires extend vertically from the surface of the semiconductor chip.
It is preferable that the coaxial body comprising the conductive wire and the resin layer covering the periphery of the conductive wire is deformable.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: providing a semiconductor chip having a plurality of bonding pads formed on a surface of the semiconductor chip; coupling a plurality of conductive wires onto the bonding pads by wire bonding such that the conductive wires extend away from the surface of the semiconductor chip; applying a resin layer on the surface of the semiconductor chip and on the periphery the plurality of conductive wires, each of the conductive wires and the resin layer covering the periphery of the conductive wire forming a coaxial body; exposing top end portion of each of the conductive wires by removing the resin layer from the upper end portion of the coaxial bodies; disposing flux with resin on the top end portions of the coaxial bodies; and disposing solder balls on the top end portions of the coaxial bodies via the flux with resin and coupling the solder balls with the conductive wires of the coaxial bodies by a reflow process; whereby flux component of the flux with resin disappears by the reflow process, and remained resin component of the flux with resin fills gaps between the solder balls and the coaxial bodies to reinforce the coupling force of the solder balls with the coaxial bodies.
In this case, it is preferable that, in the exposing the top end portion of each of the conductive wires by removing the resin layer from the upper end portion of the coaxial bodies, the resin layer is removed by grinding or etching.
It is also preferable that, in the exposing the top end portion of each of the conductive wires by removing the resin layer from the upper end portion of the coaxial bodies, top end portions of the coaxial bodies are cut away to expose the top end portion of each of the conductive wires.
It is further preferable that each of the conductive wires has a length of 300 to 1000 micrometers.
It is advantageous that the conductive wires are made of gold or gold alloy.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: providing a semiconductor chip having a plurality of bonding pads formed on a surface of the semiconductor chip; coupling a plurality of conductive wires onto the bonding pads by wire bonding such that the conductive wires extend away from the surface of the semiconductor chip; applying a resin layer on the surface of the semiconductor chip such that the plurality of conductive wires are buried in the resin layer; removing the upper portion of the resin layer to expose top end portion of each of the conductive wires, and removing the resin layer further from portions between the conductive wires while leaving the resin layer thinly at the periphery of each of the conductive wires as an upper portion coating resin layer; applying flux with resin on whole area over the semiconductor chip; disposing solder balls on the top end portions of the conductive wires via the flux with resin and coupling the solder balls with the conductive wires by a reflow process; removing the resin layer further from portions between the conductive wires while leaving the resin layer at the lower periphery of each of the conductive wires as a lower portion coating resin layer which is thicker than the upper portion coating resin layer, thereby forming a step portion between the upper portion coating resin layer and the lower portion coating resin layer; whereby flux component of the flux with resin disappears by the reflow process, and remained resin component of the flux with resin fills portions from the solder balls to the upper portion coating resin layer to reinforce the coupling force of the solder balls with the conductive wires and the upper portion coating resin layer.
In this case, it is preferable that, in the removing the upper portion of the resin layer to expose top end portion of each of the conductive wires, and removing the resin layer further from portions between the conductive wires while leaving the resin layer thinly at the periphery of each of the conductive wires as an upper portion coating resin layer, the resin layer is removed by using a dicer or a laser beam
It is also preferable that, in the removing the resin layer further from portions between the conductive wires while leaving the resin layer at the lower periphery of each of the conductive wires as a lower portion coating resin layer which is thicker than the upper portion coating resin layer, the resin layer is removed by using a dicer or a laser beam.